With a digital communication system, an error correcting code is generally utilized because the communication system makes use of a channel having a high bit error rate. The BCH code is an example of a code which may be utilized for transmitting data in a digital communication system. (See, e.g., U.S. Pat. No. 4,556,977 and U.S. Pat. No. 4,502,141).
In one example of a BCH code, data is transmitted in codewords which are 40 bits long comprising 28 data bits and 12 error correction bits. At a receiver, an error can be located in any one of the k, k=0, . . . , 39 bit positions.
It is a recent trend in the use of BCH codes, as in the above example, that a single bit error is corrected while a t-bit error (t&gt;1) is merely detected without correction, even when the BCH code is such that the correction of double errors is possible. This is because the triple error is often wrongly corrected as the double error despite the fact that the triple error actually occurs.
A conventional BCH error correction circuit receives a succession of BCH code words. The conventional error correction circuit comprises a divider for dividing each codeword by a generator polynomial to obtain a syndrome dependent on the error contained in the codeword and a circuit for determining an error location in each codeword in accordance with the syndrome when the syndrome exhibits occurrence of a single error. The single error is corrected in each codeword. The conventional error checking circuit comprises a read only memory (ROM) as the circuit for determining the error location in each codeword. Such a ROM is programmed in advance to produce an error location signal representative of the error location in the codeword in response to the syndrome. With the conventional error checking circuit, the ROM must have a great memory capacity in order to carry out the above-mentioned operation.
U.S. Pat. No. 4,502,141 describes an improved error correction circuit which requires less memory. This error correction circuit decides whether there is a single or a t-bit error (t being greater than unity) in a received BCH codeword, which codeword was originally derived using a generator polynomial that is factorable into a primitive and a non-primitive polynomial. The error correction circuit comprises first and second dividers for dividing each received codeword by the primitive and non-primitive polynomial, respectively, to provide first and second patterns of binary signals. If the received codeword includes only a single error, the first pattern of binary signals is a residue which specifies a syndrome of the single error. A different pattern of binary signals is produced by the first divider for each possible location of the single bit error in the received codeword. A memory is loaded with reference numbers corresponding to the respective non-zero residues and produces one of the reference numbers only in the presence of a single bit error. A comparator compares the produced reference number with the residue represented by the second pattern of binary signals produced by the second divider to carry out the decision as to whether or not there is in fact a single bit or a multi-bit error in the received codeword. Preferably, the memory is also loaded with the single error bit locations to locate a single bit error in a received codeword.
Thus, in short, the prior art discloses the use of an error correction scheme for BCH codewords which involves calculating one or more syndromes of the received codeword to obtain a single bit error location in the received codeword. A memory device, no matter how small, plays an essential role in the prior art BCH error correction circuits. However, the use of the memory limits the flexibility and increases the complexity of a BCH error correction circuit.
Accordingly, it is an object of the present invention to provide an error correction circuit for received BCH codewords which utilizes no memory.